/**************************************************************************//** * @file GPIO.h * @version V3.00 * $Revision: 21 $ * $Date: 15/08/11 10:26a $ * @brief M451 series GPIO driver header file * * @note * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved. * ******************************************************************************/#ifndef __GPIO_H__#define__GPIO_H__#ifdef __cplusplusextern"C"{#endif/** @addtogroup Standard_Driver Standard Driver @{*//** @addtogroup GPIO_Driver GPIO Driver @{*//** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants @{*/#defineGPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port *//*---------------------------------------------------------------------------------------------------------*//*GPIO_MODE Constant Definitions*//*---------------------------------------------------------------------------------------------------------*/#defineGPIO_MODE_INPUT 0x0UL /*!< Input Mode */#defineGPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */#defineGPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */#defineGPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode *//*---------------------------------------------------------------------------------------------------------*//*GPIO Interrupt Type Constant Definitions*//*---------------------------------------------------------------------------------------------------------*/#defineGPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */#defineGPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */#defineGPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */#defineGPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */#defineGPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level *//*---------------------------------------------------------------------------------------------------------*//*GPIO_INTTYPE Constant Definitions*//*---------------------------------------------------------------------------------------------------------*/#defineGPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */#defineGPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode *//*---------------------------------------------------------------------------------------------------------*//*GPIO_DBCTL Constant Definitions*//*---------------------------------------------------------------------------------------------------------*/#defineGPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */#defineGPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */#defineGPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */#defineGPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */#defineGPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */#defineGPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */#defineGPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */#defineGPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */#defineGPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */#defineGPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */#defineGPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */#defineGPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */#defineGPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */#defineGPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */#defineGPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */#defineGPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */#defineGPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */#defineGPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */#defineGPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */#defineGPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks *//*Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. Example 1: PA0 = 1; It is used to set GPIO PA.0 to high; Example 2: if (PA0) PA0 = 0; If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.*/#defineGPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))#definePA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */#definePA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */#definePA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */#definePA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */#definePA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */#definePA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */#definePA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */#definePA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */#definePA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */#definePA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */#definePA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */#definePA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */#definePA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */#definePA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */#definePA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */#definePA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */#definePB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */#definePB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */#definePB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */#definePB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */#definePB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */#definePB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */#definePB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */#definePB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */#definePB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */#definePB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */#definePB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */#definePB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */#definePB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */#definePB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */#definePB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */#definePB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */#definePC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */#definePC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */#definePC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */#definePC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */#definePC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */#definePC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */#definePC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */#definePC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */#definePC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */#definePC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */#definePC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */#definePC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */#definePC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */#definePC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */#definePC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */#definePC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */#definePD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */#definePD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */#definePD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */#definePD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */#definePD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */#definePD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */#definePD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */#definePD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */#definePD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */#definePD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */#definePD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */#definePD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */#definePD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */#definePD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */#definePD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */#definePD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */#definePE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */#definePE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */#definePE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */#definePE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */#definePE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */#definePE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */#definePE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */#definePE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */#definePE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */#definePE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */#definePE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */#definePE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */#definePE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */#definePE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */#definePE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */#definePF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */#definePF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */#definePF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */#definePF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */#definePF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */#definePF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */#definePF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */#definePF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output *//*@}*//*end of group GPIO_EXPORTED_CONSTANTS*//** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions @{*//** * @brief Clear GPIO Pin Interrupt Flag * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Clear the interrupt status of specified GPIO pin.*/#defineGPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))/** * @brief Disable Pin De-bounce Function * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Disable the interrupt de-bounce function of specified GPIO pin.*/#defineGPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))/** * @brief Enable Pin De-bounce Function * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * @return None * * @details Enable the interrupt de-bounce function of specified GPIO pin.*/#defineGPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))/** * @brief Disable I/O Digital Input Path * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Disable I/O digital input path of specified GPIO pin.*/#defineGPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))/** * @brief Enable I/O Digital Input Path * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Enable I/O digital input path of specified GPIO pin.*/#defineGPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))/** * @brief Disable I/O DOUT mask * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Disable I/O DOUT mask of specified GPIO pin.*/#defineGPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))/** * @brief Enable I/O DOUT mask * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @return None * * @details Enable I/O DOUT mask of specified GPIO pin.*/#defineGPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))/** * @brief Get GPIO Pin Interrupt Flag * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD. * It could be BIT0 ~ BIT14 for PE. * It could be BIT0 ~ BIT7 for PF. * * @retval 0 No interrupt at specified GPIO pin * @retval 1 The specified GPIO pin generate an interrupt * * @details Get the interrupt status of specified GPIO pin.*/#defineGPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))/** * @brief Set De-bounce Sampling Cycle Time * * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be * - \ref GPIO_DBCTL_DBCLKSEL_1 * - \ref GPIO_DBCTL_DBCLKSEL_2 * - \ref GPIO_DBCTL_DBCLKSEL_4 * - \ref GPIO_DBCTL_DBCLKSEL_8 * - \ref GPIO_DBCTL_DBCLKSEL_16 * - \ref GPIO_DBCTL_DBCLKSEL_32 * - \ref GPIO_DBCTL_DBCLKSEL_64 * - \ref GPIO_DBCTL_DBCLKSEL_128 * - \ref GPIO_DBCTL_DBCLKSEL_256 * - \ref GPIO_DBCTL_DBCLKSEL_512 * - \ref GPIO_DBCTL_DBCLKSEL_1024 * - \ref GPIO_DBCTL_DBCLKSEL_2048 * - \ref GPIO_DBCTL_DBCLKSEL_4096 * - \ref GPIO_DBCTL_DBCLKSEL_8192 * - \ref GPIO_DBCTL_DBCLKSEL_16384 * - \ref GPIO_DBCTL_DBCLKSEL_32768 * * @return None * * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, * and system will sampling interrupt input once per 00 us.*/#defineGPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))/** * @brief Get GPIO Port IN Data * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * * @return The specified port data * * @details Get the PIN register of specified GPIO port.*/#defineGPIO_GET_IN_DATA(port) ((port)->PIN)/** * @brief Set GPIO Port OUT Data * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32Data GPIO port data. * * @return None * * @details Set the Data into specified GPIO port.*/#defineGPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))/** * @brief Toggle Specified GPIO pin * * @param[in] u32Pin Pxy * * @return None * * @details Toggle the specified GPIO pint.*/#defineGPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)/** * @brief Enable External GPIO interrupt * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32Pin The pin of specified GPIO port. * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port. * It could be 0 ~ 14 for PE GPIO port. * It could be 0 ~ 7 for PF GPIO port. * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. * * @return None * * @details This function is used to enable specified GPIO pin interrupt.*/#defineGPIO_EnableEINT GPIO_EnableInt/** * @brief Disable External GPIO interrupt * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32Pin The pin of specified GPIO port. * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port. * It could be 0 ~ 14 for PE GPIO port. * It could be 0 ~ 7 for PF GPIO port. * * @return None * * @details This function is used to enable specified GPIO pin interrupt.*/#defineGPIO_DisableEINT GPIO_DisableIntvoidGPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);voidGPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);voidGPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);/*@}*//*end of group GPIO_EXPORTED_FUNCTIONS*//*@}*//*end of group GPIO_Driver*//*@}*//*end of group Standard_Driver*/#ifdef __cplusplus }#endif#endif//__GPIO_H__/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/

/**************************************************************************//** * @file gpio.c * @version V3.00 * $Revision: 6 $ * $Date: 15/08/11 10:26a $ * @brief M451 series GPIO driver source file * * @note * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. *****************************************************************************/#include"M451Series.h"/** @addtogroup Standard_Driver Standard Driver @{*//** @addtogroup GPIO_Driver GPIO Driver @{*//** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions @{*//** * @brief Set GPIO operation mode * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32PinMask The single or multiple pins of specified GPIO port. * It could be BIT0 ~ BIT15 for PA, PB, PC and PD GPIO port. * It could be BIT0 ~ BIT14 for PE GPIO port. * It could be BIT0 ~ BIT7 for PF GPIO port. * @param[in] u32Mode Operation mode. It could be \n * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. * * @return None * * @details This function is used to set specified GPIO operation mode.*/voidGPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) { uint32_t i;for(i =0; i < GPIO_PIN_MAX; i++) {if(u32PinMask & (1<<i)) { port->MODE = (port->MODE & ~(0x3<< (i <<1))) | (u32Mode << (i <<1)); } } }/** * @brief Enable GPIO interrupt * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32Pin The pin of specified GPIO port. * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port. * It could be 0 ~ 14 for PE GPIO port. * It could be 0 ~ 7 for PF GPIO port. * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. * * @return None * * @details This function is used to enable specified GPIO pin interrupt.*/voidGPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) { port->INTTYPE |= (((u32IntAttribs >>24) &0xFFUL) <<u32Pin); port->INTEN |= ((u32IntAttribs &0xFFFFFFUL) <<u32Pin); }/** * @brief Disable GPIO interrupt * * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. * @param[in] u32Pin The pin of specified GPIO port. * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port. * It could be 0 ~ 14 for PE GPIO port. * It could be 0 ~ 7 for PF GPIO port. * * @return None * * @details This function is used to enable specified GPIO pin interrupt.*/voidGPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) { port->INTTYPE &= ~(1UL<<u32Pin); port->INTEN &= ~((0x00010001UL) <<u32Pin); }/*@}*//*end of group GPIO_EXPORTED_FUNCTIONS*//*@}*//*end of group GPIO_Driver*//*@}*//*end of group Standard_Driver*//*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/

/*Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1)*/SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk |SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);

PD->MODE = (PD->MODE & (~GPIO_MODE_MODE7_Msk)) | (GPIO_MODE_INPUT << GPIO_MODE_MODE7_Pos);

PB->MODE = (PB->MODE & (~GPIO_MODE_MODE3_Msk)) | (GPIO_MODE_OUTPUT << GPIO_MODE_MODE3_Pos);

/*Configure PB.2 as Input mode and enable interrupt by rising edge trigger*/PB->MODE = (PB->MODE & (~GPIO_MODE_MODE2_Msk)) | (GPIO_MODE_INPUT <<GPIO_MODE_MODE2_Pos); PB->INTTYPE |= (GPIO_INTTYPE_EDGE <<GPIO_INTTYPE_TYPE2_Pos); PB->INTEN |=GPIO_INTEN_RHIEN2_Msk; NVIC_EnableIRQ(GPB_IRQn);/*Configure PC.5 as Quasi-bidirection mode and enable interrupt by falling edge trigger*/PC->MODE = (PC->MODE & (~GPIO_MODE_MODE5_Msk)) | (GPIO_MODE_QUASI <<GPIO_MODE_MODE5_Pos); PC->INTTYPE |= (GPIO_INTTYPE_EDGE <<GPIO_INTTYPE_TYPE5_Pos); PC->INTEN |=GPIO_INTEN_FLIEN5_Msk; NVIC_EnableIRQ(GPC_IRQn);/*Enable interrupt de-bounce function and select de-bounce sampling cycle time is 1024 clocks of LIRC clock*/GPIO->DBCTL = (GPIO_DBCTL_ICLK_ON | GPIO_DBCTL_DBCLKSRC_LIRC |GPIO_DBCTL_DBCLKSEL_1024); PB->DBEN |=BIT2; PC->DBEN |= BIT5;

typedefstruct{/** * @var GPIO_T::MODE * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[2n+1:2n]|MODEn |Port A-F I/O Pin Mode Control * | | |Determine each I/O mode of Px.n pins. * | | |00 = Px.n is in Input mode. * | | |01 = Px.n is in Push-pull Output mode. * | | |10 = Px.n is in Open-drain Output mode. * | | |11 = Px.n is in Quasi-bidirectional mode. * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be * | | |input mode after chip powered on. * | | |Note2: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::DINOFF * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[n+16] |DINOFFn |Port A-F Pin Digital Input Path Disable Control * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. * | | |0 = Px.n digital input path Enabled. * | | |1 = Px.n digital input path Disabled (digital input tied to low). * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::DOUT * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |DOUTn |Port A-F Pin Output Value * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::DATMSK * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |DMASKn |Port A-F Pin Data Output Write Mask * | | |These bits are used to protect the corresponding DOUT (Px_DOUT ) bit. * | | |When the DATMSK (Px_DATMSK ) bit is set to 1, the corresponding DOUT (Px_DOUT ) bit is protected. * | | |If the write signal is masked, writing data to the protect bit is ignored. * | | |0 = Corresponding DOUT (Px_DOUT ) bit can be updated. * | | |1 = Corresponding DOUT (Px_DOUT ) bit protected. * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT ) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. * | | |Note2: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::PIN * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |PINn |Port A-F Pin Pin Value * | | |Each bit of the register reflects the actual status of the respective Px.n pin. * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::DBEN * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |DBENn |Port A-F Pin Input Signal De-Bounce Enable Bit * | | |The DBEN bit is used to enable the de-bounce function for each corresponding bit. * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). * | | |0 = Px.n de-bounce function Disabled. * | | |1 = Px.n de-bounce function Enabled. * | | |The de-bounce function is valid only for edge triggered interrupt. * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::INTTYPE * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |TYPEn |Port A-F Pin Edge Or Level Detection Interrupt Trigger Type Control * | | |TYPE (Px_INTTYPE ) bit is used to control the triggered interrupt is by level trigger or by edge trigger. * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. * | | |0 = Edge trigger interrupt. * | | |1 = Level trigger interrupt. * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN ). * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. * | | |The de-bounce function is valid only for edge triggered interrupt. * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::INTEN * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |FLIENn |Port A-F Pin Falling Edge or Low Level Interrupt Trigger Type Enable Bit * | | |The FLIEN (Px_INTEN ) bit is used to enable the interrupt for each of the corresponding input Px.n pin. * | | |Set bit to 1 also enable the pin wake-up function. * | | |When setting the FLIEN (Px_INTEN ) bit to 1 : * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE ) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE ) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. * | | |0 = Px.n level low or high to low interrupt Disabled. * | | |1 = Px.n level low or high to low interrupt Enabled. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::INTSRC * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |INTSRCn |Port A-F Pin Interrupt Source Flag * | | |Write Operation : * | | |0 = No action. * | | |1 = Clear the corresponding pending interrupt. * | | |Read Operation : * | | |0 = No interrupt at Px.n. * | | |1 = Px.n generates an interrupt. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::SMTEN * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |SMTENn |Port A-F Pin Input Schmitt Trigger Enable Bit * | | |0 = Px.n input Schmitt trigger function Disabled. * | | |1 = Px.n input Schmitt trigger function Enabled. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::SLEWCTL * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |HSRENn |Port A-F Pin High Slew Rate Control * | | |0 = Px.n output with basic slew rate. * | | |1 = Px.n output with higher slew rate. * | | |Note: * | | |n=0~15 for port A/B/C/D. * | | |n=0~14 for port E. * | | |n=0~7 for port F. * @var GPIO_T::DRVCTL * Offset: 0x2C Port E High Drive Strength Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * | |HDRVENn |Port E Pin Driving Strength Control * | | |0 = Px.n output with basic driving strength. * | | |1 = Px.n output with high driving strength. * | | |Note: * | | |n=8,9..13 for port E.*/__IO uint32_t MODE;/*Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control*/__IO uint32_t DINOFF;/*Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control*/__IO uint32_t DOUT;/*Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value*/__IO uint32_t DATMSK;/*Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask*/__I uint32_t PIN;/*Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value*/__IO uint32_t DBEN;/*Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register*/__IO uint32_t INTTYPE;/*Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control*/__IO uint32_t INTEN;/*Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register*/__IO uint32_t INTSRC;/*Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag*/__IO uint32_t SMTEN;/*Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register*/__IO uint32_t SLEWCTL;/*Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register*/__IO uint32_t DRVCTL;/*Offset: 0x12C Port E High Drive Strength Control Register*/} GPIO_T; typedefstruct{/** * @var GPIO_DBCTL_T::DBCTL * Offset: 0x440 Interrupt De-bounce Control Register * --------------------------------------------------------------------------------------------------- * |Bits |Field |Descriptions * | :----: | :----: | :---- | * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection * | | |0000 = Sample interrupt input once per 1 clocks. * | | |0001 = Sample interrupt input once per 2 clocks. * | | |0010 = Sample interrupt input once per 4 clocks. * | | |0011 = Sample interrupt input once per 8 clocks. * | | |0100 = Sample interrupt input once per 16 clocks. * | | |0101 = Sample interrupt input once per 32 clocks. * | | |0110 = Sample interrupt input once per 64 clocks. * | | |0111 = Sample interrupt input once per 128 clocks. * | | |1000 = Sample interrupt input once per 256 clocks. * | | |1001 = Sample interrupt input once per 2*256 clocks. * | | |1010 = Sample interrupt input once per 4*256 clocks. * | | |1011 = Sample interrupt input once per 8*256 clocks. * | | |1100 = Sample interrupt input once per 16*256 clocks. * | | |1101 = Sample interrupt input once per 32*256 clocks. * | | |1110 = Sample interrupt input once per 64*256 clocks. * | | |1111 = Sample interrupt input once per 128*256 clocks. * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection * | | |0 = De-bounce counter clock source is the HCLK. * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator. * |[5] |ICLKON |Interrupt Clock On Mode * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN ) bit is set to 1. * | | |1 = All I/O pins edge detection circuit is always active after reset. * | | |Note: It is recommended to disable this bit to save system power if no special application concern.*/__IO uint32_t DBCTL;/*Offset: 0x440 Interrupt De-bounce Control Register*/} GPIO_DBCTL_T;/** @addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller @{*/#defineGPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */#defineGPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */#defineGPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */#defineGPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */#defineGPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */#defineGPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */#defineGPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */#defineGPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */#defineGPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */#defineGPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */#defineGPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */#defineGPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */#defineGPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */#defineGPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */#defineGPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */#defineGPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */#defineGPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */#defineGPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */#defineGPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */#defineGPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */#defineGPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */#defineGPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */#defineGPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */#defineGPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */#defineGPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */#defineGPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */#defineGPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */#defineGPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */#defineGPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */#defineGPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */#defineGPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */#defineGPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */#defineGPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */#defineGPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */#defineGPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */#defineGPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */#defineGPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */#defineGPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */#defineGPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */#defineGPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */#defineGPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */#defineGPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */#defineGPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */#defineGPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */#defineGPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */#defineGPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */#defineGPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */#defineGPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */#defineGPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */#defineGPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */#defineGPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */#defineGPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */#defineGPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */#defineGPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */#defineGPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */#defineGPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */#defineGPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */#defineGPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */#defineGPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */#defineGPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */#defineGPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */#defineGPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */#defineGPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */#defineGPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */#defineGPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */#defineGPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */#defineGPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */#defineGPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */#defineGPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */#defineGPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */#defineGPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */#defineGPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */#defineGPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */#defineGPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */#defineGPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */#defineGPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */#defineGPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */#defineGPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */#defineGPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */#defineGPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */#defineGPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */#defineGPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */#defineGPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */#defineGPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */#defineGPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */#defineGPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */#defineGPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */#defineGPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */#defineGPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */#defineGPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */#defineGPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */#defineGPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */#defineGPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */#defineGPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */#defineGPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */#defineGPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */#defineGPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */#defineGPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */#defineGPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */#defineGPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */#defineGPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */#defineGPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */#defineGPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */#defineGPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */#defineGPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */#defineGPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */#defineGPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */#defineGPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */#defineGPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */#defineGPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */#defineGPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */#defineGPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */#defineGPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */#defineGPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */#defineGPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */#defineGPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */#defineGPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */#defineGPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */#defineGPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */#defineGPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */#defineGPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */#defineGPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */#defineGPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */#defineGPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */#defineGPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */#defineGPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */#defineGPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */#defineGPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */#defineGPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */#defineGPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */#defineGPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */#defineGPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */#defineGPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */#defineGPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */#defineGPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */#defineGPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */#defineGPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */#defineGPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */#defineGPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */#defineGPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */#defineGPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */#defineGPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */#defineGPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */#defineGPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */#defineGPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */#defineGPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */#defineGPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */#defineGPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */#defineGPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */#defineGPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */#defineGPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */#defineGPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */#defineGPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */#defineGPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */#defineGPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */#defineGPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */#defineGPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */#defineGPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */#defineGPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */#defineGPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */#defineGPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */#defineGPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */#defineGPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */#defineGPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */#defineGPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */#defineGPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */#defineGPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */#defineGPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */#defineGPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */#defineGPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */#defineGPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */#defineGPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */#defineGPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */#defineGPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */#defineGPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */#defineGPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */#defineGPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */#defineGPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */#defineGPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */#defineGPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */#defineGPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */#defineGPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */#defineGPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */#defineGPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */#defineGPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */#defineGPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */#defineGPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */#defineGPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */#defineGPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */#defineGPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */#defineGPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */#defineGPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */#defineGPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */#defineGPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */#defineGPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */#defineGPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */#defineGPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */#defineGPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */#defineGPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */#defineGPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */#defineGPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */#defineGPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */#defineGPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */#defineGPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */#defineGPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */#defineGPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */#defineGPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */#defineGPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */#defineGPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */#defineGPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */#defineGPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */#defineGPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */#defineGPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */#defineGPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */#defineGPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */#defineGPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */#defineGPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */#defineGPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */#defineGPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */#defineGPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */#defineGPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */#defineGPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */#defineGPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */#defineGPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */#defineGPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */#defineGPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */#defineGPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */#defineGPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */#defineGPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */#defineGPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */#defineGPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */#defineGPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */#defineGPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */#defineGPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */#defineGPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */#defineGPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */#defineGPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */#defineGPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */#defineGPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */#defineGPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */#defineGPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */#defineGPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */#defineGPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */#defineGPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */#defineGPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */#defineGPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */#defineGPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */#defineGPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */#defineGPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */#defineGPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */#defineGPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */#defineGPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */#defineGPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */#defineGPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */#defineGPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */#defineGPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */#defineGPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */#defineGPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */#defineGPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */#defineGPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */#defineGPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */#defineGPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */#defineGPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */#defineGPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */#defineGPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */#defineGPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */#defineGPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */#defineGPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */#defineGPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */#defineGPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */#defineGPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */#defineGPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */#defineGPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */#defineGPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */#defineGPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */#defineGPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */#defineGPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */#defineGPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */#defineGPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */#defineGPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */#defineGPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */#defineGPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */#defineGPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */#defineGPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */#defineGPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */#defineGPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */#defineGPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */#defineGPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */#defineGPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */#defineGPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */#defineGPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */#defineGPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */#defineGPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */#defineGPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */#defineGPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */#defineGPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */#defineGPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */#defineGPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */#defineGPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */#defineGPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */#defineGPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */#defineGPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */#defineGPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */#defineGPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */#defineGPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */#defineGPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */#defineGPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */#defineGPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */#defineGPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */#defineGPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */#defineGPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */#defineGPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */#defineGPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */#defineGPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */#defineGPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */#defineGPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */#defineGPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */#defineGPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */#defineGPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */#defineGPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */#defineGPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */#defineGPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */#defineGPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */#defineGPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */#defineGPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */#defineGPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */#defineGPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */#defineGPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */#defineGPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */#defineGPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */#defineGPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */#defineGPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */#defineGPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */#defineGPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */#defineGPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */#defineGPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */#defineGPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */#defineGPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */#defineGPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */#defineGPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */#defineGPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */#defineGPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */#defineGPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */#defineGPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */#defineGPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */#defineGPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */#defineGPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */#defineGPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */#defineGPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */#defineGPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */#defineGPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */#defineGPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */#defineGPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */#defineGPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */#defineGPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */#defineGPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */#defineGPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */#defineGPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */#defineGPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */#defineGPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */#defineGPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */#defineGPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */#defineGPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */#defineGPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */#defineGPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */#defineGPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */#defineGPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */#defineGPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */#defineGPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */#defineGPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */#defineGPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */#defineGPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */#defineGPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */#defineGPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */#defineGPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */#defineGPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */#defineGPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */#defineGPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */#defineGPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */#defineGPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */#defineGPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */#defineGPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */#defineGPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */#defineGPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */#defineGPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */#defineGPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */#defineGPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */#defineGPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */#defineGPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */#defineGPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */#defineGPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */#defineGPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */#defineGPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */#defineGPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */#defineGPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */#defineGPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */#defineGPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */#defineGPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */#defineGPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */#defineGPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */#defineGPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */#defineGPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask *//**@}*//*GPIO_CONST*//**@}*//*end of GPIO register group*/

PB->MODE = (PB->MODE & (~GPIO_MODE_MODE2_Msk)) | (GPIO_MODE_INPUT << GPIO_MODE_MODE2_Pos);